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| PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z89320 16-BIT DSP DIGITAL SIGNAL PROCESSOR GENERAL DESCRIPTION The Z89320 is a second generation, 16-bit fractional, two's complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are accomplished in a single clock cycle. The processor contains 1Kbyte of on-chip data RAM (two blocks of 256 16-bit words), 4K words of program ROM. Also, the processor features a 24-bit ALU, a 16x16 multiplier, a 24bit Accumulator and a shifter. Additionally, the processor contains a six-level stack, three vectored interrupts and two inputs for conditional program jumps. Each RAM block contains a set of three pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simultaneously addressed and loaded to the multiplier for a true single cycle multiply. The device includes a 16-bit I/O bus for transferring data or for mapping peripherals into the processor address space. Additionally, there are two general purpose user inputs and two user outputs. Operation with slow peripherals is accompished with a ready input pin. Development tools for the IBM PC include a relocatable assembler, a linker loader, and an ANSI-C compiler. Also, the development tools include a simulator/debugger, a cross assembler for the TMS320 family assembly code and a hardware emulator. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS DC-4128-00 (12-2-92) 1 GENERAL DESCRIPTION (Continued) Register Pointer 4-6 PC Instruction Register 4K Word ROM Register Pointer 0-2 256 Word RAM 0 256 Word RAM 1 16 EXT0-15 16-Bit Bus Switch S-Bus X 16 x16 Multiplier 24-bit P 24 24-Bit Bus P Bus Interrupt 3 INTO-2 /RESET MUX Shifter Status (5) User Port Y Switch Stack Ready D Bus 16-bit I/O Port 3 /RDYE, ER//W, /EI EA0-2 2 2 UI0-1 UO0-1 B ALU A ACC Functional Block Diagram 2 PIN DESCRIPTION EXT12 EXT13 EXT14 VSS EXT15 EXT3 EXT4 VSS EXT5 EXT6 EXT7 EXT8 EXT9 VSS EXT10 EXT11 INT2 INT1 UI1 UI0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 VSS EXT2 EXT1 EXT0 VSS NC (must be VSS) UO1 UO0 INT0 HALT CK /EI VDD EA2 EA1 EA0 /RES /RDYE ER//W VDD Z89320 30 29 28 27 26 25 24 23 22 21 40-Pin DIP Pin Assignments 3 PIN DESCRIPTION (Continued) HALT INT0 UO0 VDD EA2 EA1 Uo1 NC NC CK /EI 6 VSS EXT0 EXT1 EXT2 VSS N/C EXT12 EXT13 EXT14 VSS EXT15 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 EA0 /RES /RDYE ER//W VDD NC UI0 UI1 INT1 INT2 EXT11 Z89320 PLCC 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 EXT3 EXT4 EXT9 VSS EXT7 EXT5 EXT6 EXT8 VSS NC 44-Pin PLCC Pin Assignments (Standard Mode) 4 EXT10 ABSOLUTE MAXIMUM RATINGS Storage temperature range Lead temperature (if packaged) VDD Voltage to VSS All other pins -65C to +150C 300C for 10 sec. -0.5 to 7.0V VDD+0.5V to VSS-0.5V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Test Load Diagram). From Output Under Test +5V 2.1 K 150 pF 9.1 K Test Load Diagram DC ELECTRICAL CHARACTERISTICS (VDD= 5V 5%, TA = 0C to +70C unless otherwise specified) Symbol IDD IDC VIH VIL IL VOH VOL IFL Parameter Supply Current DC Power Consumption Input High Level Input Low Level Input Leakage Output High Voltage Output Low Voltage Output Floating Leakage Current IOH=-100 A IOL=0.5 mA Condition VDD=5.25V fclock=10 MHz VDD=5.25V Min. Max. 40 1 mA 0.9 VDD 0.1 VDD 1 VDD-0.2 0.5 5 5 Units mA mA V V A V V A 5 AC TIMING DIAGRAM TXWH TCY PWW TXVD CK TEAD TIED TIED /EI TEAD ER//W EXT Bus: Output EXT (15:0) Valid Data Out EA (2:0) Valid Address Out TEAD RDYS RDYH /RDYE WRITE to external device timing TXRH TCY PWW TXRS CK TEAD TIED TIED /EI ER//W EXT Bus: Input Valid Data In EXT (15:0) EA (2:0) Valid Address Out TEAD RDYS RDYH /RDYE READ from external device timing 6 AC ELECTRICAL CHARACTERISTICS (VDD = 5V 5%, TA = 0C to +70C unless otherwise specified) Symbol TCY PWW Tr Tf TEAD TXVD TXWH TXRS TXRH TIED RDYS RDYH Parameter Clock Cycle Time Clock Pulse Width Clock Rise Time Clock Fall Time EA,ER//W Delay from CK EXT Data Output Valid from CK EXT Data Output Hold from CK EXT Data Input Setup Time EXT Data Input Hold from CK /EI Delay Time from CK Ready Setup Time Ready Hold Time Min. 100 45 2 2 15 5 15 15 0 0 10 0 Max. 1000 4 4 25 25 Units ns ns ns ns ns ns ns ns ns ns ns ns 15 5 Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. IBM is a registered trademark of International Business Machines Corporation. (c) 1992 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of mer- chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 7 |
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